Digital clock signals are commonly used to synchronize functionality of circuit components in a variety of applications. In some applications, a clock signal is provided along with copies of the signal shifted in phase by various offsets. For example, in a phase locked loop, a voltage controlled oscillator (VCO) may provide a four-bit output corresponding to periodic binary clock signal and versions of that clock signal shifted by 90, 180, and 270 degrees, respectively. In some contexts, such a four-bit signal (which may equivalently be considered as four one-bit signals) may be used to generate a lower frequency clock, e.g., using a clock divider such as a divide-by-2 circuit. For example, the four-bit VCO output may be processed by a divide-by-2 circuit to yield an eight-bit signal at half the frequency of the four bit signal. In other words, the four bits of the VCO output, which may be considered as four one-bit signals at 0, 90, 180, and 270 degrees phase offset, respectively, is processed to yield eight one-bit signals at phase offsets of 0, 45, 90, 135, 180, 225, 270, and 315 degrees, respectively, each at half the frequency of the original four signals.
Such a divide-by-two circuit may be implemented using a logic element such as a D flip-flop (DFF). A DFF has a data (D) input, an output Q and its complementary output QBAR, where QBAR may be coupled to the D input, a clock input, and an enable input. The DFF is triggered on a clock edge (e.g., a positive edge of the clock input, representing a transition from logic ‘0’ to logic ‘1’) so that the value at the D input (the value at QBAR before the edge) is provided as output Q. When a periodic clock signal with frequency f is provided as the clock input, the Q output is a periodic clock signal with frequency f/2.
Four such divide-by-two circuits may implement the example described above regarding VCO output signals at phase offsets of 0, 90, and 180 and 270 degrees, referred to as HF0, HF90, HF180, and HF270 because they are relatively high frequency. A first divide-by-two circuit processes HF0 to yield a lower frequency (half the frequency of HF0) signal LF0 and its 180-degree-shifted variant LF180 (because the Q and QBAR outputs of a DFF are 180 degrees out of phase); a second divide-by-two circuit processes HF90 to yield LF45 and LF225; a third divide-by-two circuit processes HF180 to yield LF90 and LF270; and a fourth divide-by-two circuit processes HF270 to yield LF135 and LF315.
Timing of the activation (enabling) of divide-by-two circuits affects the functionality in such an implementation. A DFF that implements a divide-by-two circuit may initially be in one of two states, and the output of the DFF depends on the initial state. Therefore, there are two possibilities for the output, one correct and one incorrect, In other words, activating the four DFFs described above during the wrong time interval may cause the output signals of the DFFs to not have the desired phase relationship. For example, suppose HF0 has period T and has a rising edge at time tr. If the four DFFs that implement the divide-by-two circuits are enabled during the quarter period preceding that rising edge (i.e., between times tr−T/4 and tr), then the LF0, LF45, LF90 and LF135 outputs provided by respective divide-by-two circuits may have the correct (desired) phase relationships, i.e., a rising edge of LF0 aligned with the rising edge of HF0 at time tr, a rising edge of LF45 at time tr+T/4 to trail LF0 by 45 degrees, a rising edge of LF90 at time tr+T/2 to trail LF0 by 90 degrees, and a rising edge of LF135 at time tr+3T/2 to trail LF0 by 135 degrees. However, if the DFFs are enabled during the wrong interval (e.g., between times tr and tr+T/2), the outputs of the divide-by-two circuits may not have the correct phase relationships. If the outputs of the divide-by-two circuits are out of phase, timing errors may propagate to other circuit elements.